SIMPLE AS POSSIBLE SAP-1

SAP is Simple As Possible Computer. The type of computer is specially designed for the academic purpose and nothing has to do with the commercial use. The architecture is 8 bits and comprises of 16 X 8 memory i.e. 16 memory location with 8 bits in each location, therefore, need 4 address lines which either comes from the PC (Program Counter whish may be called instruction pointer) during computer run phase or may comes from the 4 address switches during the program phase. All intructions (5 only) stores in this memory. It means SAP cann't store program having more than 16 instructions. 
SAP can only perform addition and subtraction and no logical operation. These arithematic operation are performed by an adder/subtractor unit. 
There is one general purpose register (B register) used to hold one operand of the arithmatic operation while another is kept by the accumulator register of the SAP-1. 
In addition there are 8 LEDs, work as output unit and connected with the 8 bit output register. 
All timely moment of data or activities are performed by the controller/sequencer part of the SAP-1. 

A simple thought about SAP-1

The Simple-As-Possible (SAP)-1 computer is a basic model of a microprocessor. The SAP-1 design contains the basic necessities for a functional Microprocessor. Its primary purpose is to develop a basic understanding of how microprocessor works, interacts with memory and other parts of the Fig:-Architecture of sap-1 system like input and output. The
instruction set is very limited and is simple.                

The attributes in SAP-1 computer are

● W bus - A single 8 bit bus for address and data transfer.
● 16 Bytes memory (RAM)
● Registers are accumulator and B-register each of 8 bits.
● Program counter – initializes from 00H(0d) to FFH(15d) during program execution.
● Memory Address Register (MAR) to store memory addresses.
● Adder/Subtracter for addition and subtraction instructions.
● A Control Unit
● A Simple Output.
● 6 machine reserved for each instruction

The instruction format of SAP-1 Computer is

(XXXX) (XXXX)

the first four bits make the opcode while the last four bits make the address.

SAP-1 instruction set consists of following instructions

Mnemonic---Operation---OPCODE
LDA---Load addressed memory contents into accumulator---0000
ADD---Add addressed memory contents to accumulator---0001
SUB---Subtract addressed memory contents from accumulator---0010
OUT---Load accumulator data into output register---1110
HLT---Stop processing---1111


Machine cycle and Instruction cycle

SAP1 has six T-states (three fetch and three execute cycles) reserved for each instruction. Not all instructions require all the six T-states for execution. The unused T- state is marked as No Operation (NOP) cycle. Each T-state is called a machine cycle for SAP1. A ring counter is used to generate a T-state at every falling edge of clock pulse. The ring counter output is reset after the 6th T-state.

FETCH CYCLE – T1, T2, T3 machine cycle
EXECUTE CYCLE - T4, T5, T6 machine cycle

Architecture of SAP-1
components SAP 1

1) Program counter 
2) Input MAR 
3) The RAM 
4) Instruction Register 
5) Controller Sequencer 
6) Accumulator 
7) The Adder-subtrector 
8) B Register 
9) Output Register 
10) Binary Display.

1. Program Counter (PC)
- it counts from 0000 to 1111 and it signals the memory address of next instruction to be fetch and executed. program counter is a register that has the address of next instruction that has to be executed after currently executing instruction. it is used for proper execution of functions of computer by providing address of next instruction to microprocessor.



2. Input and MAR (MAR)
- during a computer run, the address in the PC is latched in Memory Address Register (MAR).

3. RAM
- the program code to be executed and data for SAP-1 computer is stored here.
- during the a computer run, the RAM receives 4-bit addresses from MAR and a read operation is preformed. Also, the instruction or data word stored in RAM in placed on W bus for use by some other part of the computer.

4. Instruction Register (IR)
- IR contains the instruction, composed of OPCODE + ADDRESS, to be executed by SAP-1 computer.

5. Controller Sequencer-
- it generates the control signals for each block so that action occur in desired sequence. CLK signal is used to synchronize the overall operation of the SAP-1 computer.
- a 12-bit word comes out of the Controller- Sequencer block. This control word determines how the registers will react to the next positive CLK edge.

6. Accumulator
- it is a 8-bit buffer register that stores intermediate results during a computer run.
- it is always one of the operands of ADD, SUB and OUT instructions.

7. Adder-Subtracter
- it is a 2's complement adder-subtractor
- this module is asynchronous, which means that its contents can change as soon as the input word change.

8. B Register
- it is 8-bit buffer register which is primarily used to hold the other operand of mathematical operations.

9. Output Register
- this register hold the output of OUT instruction.

10. Binary Display
- it is a row of eight LEDs to show the contents of output register.